发明名称 |
TIMING BOTTLENECK ANALYSIS ACROSS PIPELINES TO GUIDE OPTIMIZATION WITH USEFUL SKEW |
摘要 |
Techniques and systems for guiding circuit optimization are described. Some embodiments compute a set of aggregate slacks for a set of chains of logic paths in a circuit design. Each chain of logic paths starts from a primary input or a sequential circuit element that only launches a signal but does not capture a signal and ends at a primary output or a sequential circuit element that only captures a signal but does not launch a signal. Next, the embodiments guide circuit optimization of the circuit design based on the set of aggregate slacks. |
申请公布号 |
US2014181779(A1) |
申请公布日期 |
2014.06.26 |
申请号 |
US201314141280 |
申请日期 |
2013.12.26 |
申请人 |
Synopsys, Inc. |
发明人 |
Cao Aiqun |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
1. A method for guiding circuit optimization, the method comprising:
computing a set of aggregate slacks for a set of chains of logic paths in a circuit design, wherein each chain of logic paths starts from a primary input or a sequential circuit element that only launches a signal but does not capture a signal and ends at a primary output or a sequential circuit element that only captures a signal but does not launch a signal; and guiding circuit optimization of the circuit design based on the set of aggregate slacks. |
地址 |
Mountain View CA US |