CACHE POLICIES FOR UNCACHEABLE MEMORY REQUESTS

摘要

Systems, processors, and methods for keeping uncacheable data coherent. A processor includes a multi-level cache hierarchy, and uncacheable load memory operations can be cached at any level of the cache hierarchy. If an uncacheable load misses in the L2 cache, then allocation of the uncacheable load will be restricted to a subset of the ways of the L2 cache. If an uncacheable store memory operation hits in the L1 cache, then the hit cache line can be updated with the data from the memory operation. If the uncacheable store misses in the L1 cache, then the uncacheable store is sent to a core interface unit.;Multiple contiguous store misses are merged into larger blocks of data in the core interface unit before being sent to the L2 cache.

主权项

1. A processor comprising:
one or more cores; and a plurality of levels of cache, wherein the plurality of levels of cache comprise a level one (L1) cache and a level two (L2) cache; wherein the processor is coupled to a memory, wherein an address space of the memory is partitioned into two or more regions, wherein a first region is defined as a cacheable region, wherein a second region is defined as an uncacheable region, and wherein the processor is configured to: allow uncacheable loads to be cached at any level of cache;
restrict a first uncacheable load to a predetermined subset of ways of a plurality of ways of the L2 cache responsive to detecting a miss for the first uncacheable load in the L2 cache.