发明名称 PATTERNING OF VERTICAL NANOWIRE TRANSISTOR CHANNEL AND GATE WITH DIRECTED SELF ASSEMBLY
摘要 Directed self-assembly (DSA) material, or di-block co-polymer, to pattern features that ultimately define a channel region a gate electrode of a vertical nanowire transistor, potentially based on one lithographic operation. In embodiments, DSA material is confined within a guide opening patterned using convention lithography. In embodiments, channel regions and gate electrode materials are aligned to edges of segregated regions within the DSA material.
申请公布号 WO2014098990(A1) 申请公布日期 2014.06.26
申请号 WO2013US46899 申请日期 2013.06.20
申请人 INTEL CORPORATION 发明人 NYHUS, PAUL A.;SIVAKUMAR, SWAMINATHAN
分类号 H01L21/336;H01L21/027;H01L29/78 主分类号 H01L21/336
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