| 摘要 |
A primary differential input pair of transistors (310) and a secondary differential input pair of transistors (338) are capable of operating in parallel to provide load current. A level-shifting pre-stage (384 and 387) to the secondary differential pair (338) downwardly level-shifts rail-to- rail input signals. Doing so prevents the secondary differential pair (338) from entering cut-off. A tail current shunt device (381) provides tail current to the secondary differential pair (338) as the primary differential pair (310) approaches cut-off when a common-mode component of the input signals approaches the positive voltage rail (363). Consequently, the sum of currents through first differential input transistors (315 and 342) associated with the primary and secondary differential input pairs (310 and 338) remains constant to the first load (323). Likewise, the sum of currents through the second differential input transistors (320 and 346) associated with the primary and secondary differential input pairs (310 and 338) remains constant to the second load 327). Both arms of the composite differential input stage present constant transconductances to their respective loads as a result. |
