发明名称 DEFECT OCCURRENCE PROCESS ANALYSIS DEVICE AND DEFECT OCCURRENCE PROCESS ANALYSIS METHOD
摘要 <p>This defect occurrence process analysis device is provided with: a mapping unit (521) which maps final defect information obtained in a final inspection process to coordinates set on a member according to defect type; an association unit (522) which associates intermediate defect information obtained in an intermediate inspection process and corrected result information obtained after a correction process for a defect detected in the intermediate inspection process has been performed with each other; a classification mapping unit (524) which, on the basis of the result of the classification of the intermediate defect information by a classification unit (523), maps the intermediate defect information to the coordinates set on the member according to the corrected result information; and a map display unit (525) which displays respective maps generated by the mapping unit (521) and the classification mapping unit (524) on the process-by-process basis. The present invention is applicable to manufacturing processes for an organic EL display panel and a liquid crystal display panel.</p>
申请公布号 WO2014097827(A1) 申请公布日期 2014.06.26
申请号 WO2013JP81641 申请日期 2013.11.25
申请人 SHARP KABUSHIKI KAISHA 发明人 KYOHO, MASANORI
分类号 G01M11/00;G01N21/956;G02F1/13 主分类号 G01M11/00
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