HARDWARE COMMAND TRAINING FOR MEMORY USING WRITE LEVELING MECHANISM

摘要

A method of training a command signal for a memory module. The method includes programming a memory controller into a mode wherein a single bit of an address signal is active for a single clock cycle. The method then programs a programmable delay line of the address signal with a delay value and performs initialization of the memory module. The memory module is then placed in a write leveling mode. A write leveling procedure is then performed and a response thereto is determined from the memory module. A determination is made whether the memory module is in a pass state or an error state based on the response.

主权项

1. A method of training a command signal for a memory module, said method comprising:
a) programming a memory controller into a mode wherein a single bit of an address signal is active for a single clock cycle; b) programming a programmable delay line of said address signal with a delay value; c) initializing of said memory module; d) placing said memory module in a write leveling mode; e) performing a write leveling procedure and determining a response thereto from said memory module; and f) determining whether said memory module is in a pass state or an error state based on said response.