发明名称 |
Reconfigurable logic block |
摘要 |
<p>A programmable logic device includes logic blocks such as a logic array blocks (LAB) that can be configured as a random access memory (RAM) or as a lookup table (LUT). A mode flag is provided to indicate the mode of operation of configuration logic such as a configuration RAM (CRAM) used during partial reconfiguration of a logic block. An enable read flag is provided to indicate if values stored in the configuration logic are to be read out or a known state is to be read out during a data verification process. Thus, exclusion and inclusion of portions of a region of configuration logic from data verification and correction processes allow a region of configuration logic to store both a design state and a user defined state. Moreover, the region of configuration logic may be dynamically reconfigured from one state to another without causing verification errors.</p> |
申请公布号 |
EP2541773(B1) |
申请公布日期 |
2014.06.25 |
申请号 |
EP20120173510 |
申请日期 |
2012.06.26 |
申请人 |
ALTERA CORPORATION |
发明人 |
MENDEL, DAVID W.;LAI, GARY;ZHOU, LU;PEDERSEN, BRUCE B. |
分类号 |
H03K19/177;G06F11/10 |
主分类号 |
H03K19/177 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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