| 摘要 |
<p>A method of fabricating an In-Plane Switching (IPS) screen electrode is proposed so as to address the problem in the prior art that concurrent fabrication of both a pixel ITO layer and a common ITO layer may result in a lowered spacing between the respective ITO layers, which may easily cause a short circuit. In the method, firstly a first ITO layer is etched, and the etched first ITO layer is annealed, then a second ITO layer is etched, and finally the etched first ITO layer and the etched second ITO layer are annealed concurrently. With this method, the etched first ITO layer is annealed after the first ITO layer is etched, subsequent etching of the second ITO layer will have no influence upon the annealed first ITO layer, thus making it possible to ensure the line widths of the two ITO layers and a spacing between the respective ITO layers to thereby effectively avoid the problem of a short circuit due to a too small spacing between the respective ITO layers.</p> |
