Dynamic LDPC code rate solution

摘要

The subject technology includes adjusting an error correcting code rate in a solid-state drive. A first plurality of memory operations are performed on a flash memory device of the solid-state drive using a first code rate. During operation of the drive, a controller monitors an operating condition associated with one or more memory units of the flash memory device for a trigger event. On the trigger event, the first code rate is adjusted in accordance with the operating condition to produce a second code rate, and a second plurality of memory operations is performed on the flash memory device using the second code rate.

主权项

1. A method for adjusting a code rate in a solid-state drive, the method comprising:
storing host data in a first plurality of memory units of a flash memory device using a first code rate; monitoring an operating condition associated with the flash memory device for a trigger event; adjusting, on the trigger event, the first code rate in accordance with the operating condition to produce a second code rate; and storing host data in a second plurality of memory units of the flash memory device using the second code rate.