| 摘要 |
<p>A memory unit comprising a plurality of memory cells 10, (preferably SRAM memory cells) each memory cell 10 being operatively connected to data input and output circuitry by a pair of bit lines BLAn, BLBn, (local bit lines) a pre-charge circuit 150 configured to provide a voltage for charging the bit lines, and a multiplexer circuit 140, and controller 144. The multiplexer circuit 140 comprises, for each bit line, an associated NMOS 142a, 142b device that is configured to selectively connect the bit line BLAn (BLBn), to the data input and output circuitry MA (MB) (or global bit lines) and to the pre-charge circuit 150 when activated by a corresponding bit line selection signal SEL_n, and a multiplexer controller 144 that is configured to be able to select each pair of bit lines by activating the associated NMOS devices using the corresponding bit line selection signals. Each memory cell also has an associated word line connection WL_N. The multiplexer may be configured such that the threshold voltage of the NMOS device is equal or less than that of the SRAM cell access device. (16a,b figure 1). The precharge circuit may comprise of a PMOS device 151a, 151b configured to connect to a positive supply voltage. The circuit also may also comprise of a sense amplifier and a tri-state data driver (figure 8).</p> |
