Multiple bitcells tracking scheme semiconductor memory array

摘要

A read tracking system and method for advanced memory devices are provided. The read tracking system and method include tracking multiple tracking bit cells in multiple segments and columns to incorporate device performance variation of bit cells in the memory array. The tracking path mimics the worst-case read path with some built-in margins to sufficiently and efficiently cover the read times of bit cells in a memory array without unnecessarily sacrificing the read speed performance of the memory array. A number of tracking cells may be placed at different segments and both sides of the memory array to cover read time variation across memory array.

主权项

1. A semiconductor memory array, comprising:
a first segment having first two memory banks, wherein each of the first two memory banks includes a first plurality of memory cells arranged in rows and columns, and wherein at least two first read tracking cells are disposed in at least two first read tracking columns; a second segment having second two memory banks, wherein each of the second two memory banks includes a second plurality of memory cells arranged in rows and columns, and wherein at least two second read tracking cells are disposed in at least two second read tracking columns; and a plurality of read tracking circuits coupled to the at least two first read tracking cells and the at least two second read tracking cells, wherein the plurality of read tracking circuits mimic a worst-case read path of a corner memory cell in the semiconductor memory array with built-in margins for signal lines and signal devices, wherein outputs of the at least two first read tracking cells and the at least two second read tracking cells are connected to a tracking bit connection line (TBCL), wherein a tracking circuit connected to the TBCL outputs a tracking-cells output signal to generate a global tracking result signal to a memory control circuitry, wherein the memory control circuitry is configured to set a memory clock based on the global tracking result signal.