发明名称 DECODING APPARATUS AND METHOD FOR PARALLEL PROCESSING
摘要 Disclosed are an apparatus and a method for parallel process decoding. The apparatus for parallel process decoding includes: a first decoder for receiving a first block including first N (N is an integer) bits, second N bits and third N bits, and decoding the received first block; a second decoder for receiving a second block including the third N bits, fourth N bits and fifth N bits to decode the received second block, the third N bits being decoded while the first decoder decodes the second N bits; and a third decoder for receiving a third block including the fifth N bits, sixth N bits and seventh N bits to decode the received third block, the fifth N bits being decoded while the second decoder decodes the fourth N bits.
申请公布号 KR20140077692(A) 申请公布日期 2014.06.24
申请号 KR20120146766 申请日期 2012.12.14
申请人 ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE 发明人 KIM, JEE HOON;OH, JONG EE;LEE, SOK KYU
分类号 H03M9/00 主分类号 H03M9/00
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