Variable-length code (VLC) bitstream parsing in a multi-core processor with buffer overlap regions

摘要

An information handling system includes a multi-core processor that processes variable-length code (VLC) bitstream data. The bitstream data includes multiple codewords that the processor organizes into functionally common subsets. The processor includes a general purpose processor (GPU) and one or more special purpose processor (SPUs). An SPU of the processor may includes two SPU buffers. The processor first transfers bitstream data into GPU buffer memory and then populates the SPU buffers one after another with bitstream data. The SPU buffers may each include an overlap region that the SPU populates with the same bitstream data. The SPU parses the bitstream data in the SPU buffers in alternating fashion. The SPU may shift parsing from the one SPU buffer to the other SPU buffer when parsing reaches a subset boundary within an overlap region.

主权项

1. A method of parsing a variable-length code (VLC) bitstream, comprising:
receiving, by a general purpose unit (GPU) of a processor, a VLC bitstream; storing, by the GPU, the VLC bitstream in first and second GPU buffers in the GPU; transmitting, by the GPU, the VLC bitstream to a particular special purpose unit (SPU) of a plurality of SPUs in the processor, the particular SPU including first and second SPU buffers, wherein the transmitting the VLC bitstream includes transmitting, by the first and second GPU buffers, the VLC bitstream to the particular SPU in alternating fashion between the first and second GPU buffers; receiving the VLC bitstream, by the particular special purpose unit (SPU), the particular SPU thus providing a received VLC bitstream including data; populating, by the particular special purpose unit (SPU), the first SPU buffer with the received VLC bitstream and the second SPU buffer with the received VLC bitstream, the first SPU buffer including a start address and an end address, the second SPU buffer including a start address and an end address, the first SPU buffer including a first overlap region adjacent the end address of the first SPU buffer, the first overlap region storing a portion of the received VLC bitstream, the second SPU buffer including a second overlap region adjacent the start address of the second SPU buffer, the second overlap region storing the same portion of the received VLC bitstream as the first overlap region, the first SPU buffer including a third overlap region adjacent the start address of the first SPU buffer, the third overlap region storing another portion of the received VLC bitstream, the second SPU buffer including a fourth overlap region adjacent the end address of the second SPU buffer, the fourth overlap region storing the same portion of the received VLC bitstream as the third overlap region, the particular SPU populating the second SPU buffer while decoding the first SPU buffer, the particular SPU populating the first SPU buffer while decoding the second SPU buffer, thus populating and decoding the first and second SPU buffers in alternating fashion, shifting decoding, by the particular SPU, from the first overlap region of the first SPU buffer directly to identical information in the second overlap region of the second SPU buffer when decoding reaches a subset boundary within the first overlap region in the first SPU buffer; and shifting decoding, by the particular SPU, from the fourth overlap region of the second SPU buffer directly to identical information in the third overlap region of the first SPU buffer when decoding reaches a subset boundary within the fourth overlap region in the second SPU buffer.