Thin film transistor and method for manufacturing thereof

摘要

A thin-film transistor (TFT) includes a gate electrode, a gate dielectric layer, a semiconductor layer, source/drain electrodes, a passivation layer and a protection layer. The gate electrode is disposed on a substrate. The gate dielectric layer covers the gate electrode and the substrate. The semiconductor layer is disposed on the gate dielectric layer and above the gate electrode. The semiconductor layer has a channel region disposed above the gate electrode and source/drain regions disposed at both sides of the channel region. The source/drain electrodes are disposed on the source/drain regions of the semiconductor layer and each has a barrier layer disposed on the source/drain regions of the semiconductor layer and a conductive layer disposed on the barrier layer. The passivation layer is disposed over the surface of the source/drain electrodes. The protection layer is disposed over the substrate, the passivation layer, and the channel region of the semiconductor layer.

主权项

1. A thin film transistor disposed on a substrate, comprising:
a gate electrode disposed on the substrate; a gate dielectric layer covering the gate electrode and the substrate; a patterned semiconductor layer disposed on the gate dielectric layer over the gate electrode, having a channel region disposed over the gate electrode and source/drain regions disposed at both sides of the channel region; source/drain electrodes disposed on the source/drain regions of the patterned semiconductor layer, the source/drain electrodes comprising a stack of a patterned barrier layer and a patterned metal conductive layer, the patterned barrier layer being disposed on the source/drain regions of the patterned semiconductor layer, the patterned metal conductive layer being disposed on the patterned barrier layer and in contact with the patterned barrier layer; a passivation layer made of a material consisting essentially of a metal nitride, the passivation layer covering a top surface of the patterned metal conductive layer, wherein the passivation layer has a thickness of 5-200 angstrom; and a protection layer covering the passivation layer, the channel region of the semiconductor layer, and the substrate.