Thin film transistor array panel and method of manufacturing the same

摘要

A thin film transistor (“TFT”) array panel is provided. The TFT array panel includes an insulation substrate, a gate line formed on the insulation substrate and including a gate electrode, a data line insulated from and intersecting the gate line, and including a source electrode, a drain electrode opposite to the source electrode on the gate line, and a semiconductor formed in a layer between the data line and the gate line, and having a protruding portion extending below the drain electrode, wherein a portion of the semiconductor extending towards the drain electrode, from an area occupied by the data line, is positioned within an occupying area of the gate line including the gate electrode.

主权项

1. A thin film transistor array panel comprising:
an insulation substrate extending in a plane substantially parallel to X and Y directions; a gate line formed on the insulation substrate and including a gate electrode; a data line insulated from and intersecting the gate line, and including a source electrode; a drain electrode disposed opposite to the source electrode; and a semiconductor formed in a layer between the data line and the gate line in a Z direction perpendicular to the X and Y directions, the semiconductor having a linear portion extending along the data line in the Y direction and disposed below the data line in the Z direction and having a protruding portion protruding from the linear portion in a direction substantially parallel to the plane substantially parallel to the X and Y direction and disposed below the drain electrode in the Z direction, wherein the entire area of the protruding portion of the semiconductor in the plane substantially parallel to the X and Y direction overlaps an occupying area of the gate line including the gate electrode so that the gate line covers the entire protruding portion of the semiconductor in the plane substantially parallel to the X and Y directions to block light from outside in the Z direction reaching the protruding portion of the semiconductor, and wherein an entire outer periphery defining the entire drain electrode in the plan view is disposed within an outer boundary of an occupying area of the gate line including the gate electrode in the plan view.