发明名称 |
System and method for detecting one or more winding paths for patterns on a reticle for the manufacture of semiconductor integrated circuits |
摘要 |
A system and method for detecting an invalid winding path in a layout design file includes generating a first reticle pattern file using a first path generation program, generating a second reticle pattern file using a second path generation program, comparing the first and second reticle patterns files to detect the invalid winding path. The invalid winding path includes one or more overlapping polygons. |
申请公布号 |
US8762902(B2) |
申请公布日期 |
2014.06.24 |
申请号 |
US200912649278 |
申请日期 |
2009.12.29 |
申请人 |
Semiconductor Manufacturing International (Shanghai) Corporation;Semiconductor Manufacturing International (Beijing) Corporation |
发明人 |
Yu Kuei Mei |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
Kilpatrick Townsend & Stockton LLP |
代理人 |
Kilpatrick Townsend & Stockton LLP |
主权项 |
1. A method for a computer system for detecting an invalid winding path in a layout design for the manufacture of electronic devices, the invalid winding path including one or more overlapping polygons, the computer system having one or more processors, a computer-readable storage device, and a user interface device, the method comprising:
providing a layout design file having at least one pattern layer, the at least one pattern layer having a winding path; generating a first reticle pattern from the winding path using a first calculation scheme by means of the one or more processors; generating a second reticle pattern from the winding path using a second calculation scheme by means of the one or more processors; comparing the first reticle pattern with the second reticle pattern; and in the event that there is no match: outputting a text message indicating a presence of one or more overlapping polygons; and in the event that there is a match: generating a reticle pattern file.
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地址 |
Shanghai CN |