| 摘要 |
According to one embodiment, a multicore processor system includes: a memory region, and a multicore processor that includes plural cores, a first cache, and a second cache shared between the plural cores. The memory region permits first state in which exclusive use by using the first and second cache is granted to one core, second state in which exclusive use by using the second cache is granted to one core group, and third state in which use by using neither the first cache nor the second cache is granted to all core groups. A kernel unit writes back a first cache to the second cache when a transition of the memory region from the first state to the second state is made, and writes back a second cache to the memory region when a transition of the memory region from the second state to the third state is made. |
| 主权项 |
1. A multicore processor system comprising:
a memory including a memory region; and a multicore processor including:
a plurality of processor cores;a first cache corresponding to each one of the processor cores;a second cache shared between the processor cores, in which processor cores that share a mapping setting to the memory region form a core group; andan address translation unit configured to manage the mapping setting for each of the processor cores, wherein the memory region permits:
a first state in which reading and writing by a first access by using both the first cache and the second cache is permitted, and in which only one processor core among the processor cores is permitted to use the memory;a second state in which reading and writing by a second access by not using the first cache but by using the second cache is permitted, and in which all of the processor cores belonging to only one core group are permitted to use the memory region; anda third state in which reading and writing by a third access by not using either the first cache or the second cache is permitted, and in which all of the processor cores are permitted to use the memory region, wherein the multicore processor comprises a kernel unit that makes transition of the memory region between the first state and the second state and between the second state and the third state, the kernel unit writes back the first cache corresponding to the first state to the second cache when the kernel unit makes a transition of the memory region from the first state to the second state, and writes back the second cache corresponding to the second state to the memory region when the kernel unit makes a transition of the memory region from the second state to the third state, and the address translation unit maps a plurality of virtual addresses to a physical address of the memory region for each state of the memory region, and each one of the processor cores uses a virtual address among the virtual addresses according to the state of the memory region.
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