发明名称 Digital receivers
摘要 A clock generator generates a clock signal used for sampling a received signal by a comparator which compares the received signal to a reference. A phase shifter adjusts the phase of the first clock signal and a controller adjusts the phase of the clock signal to maximize the vertical eye opening of the signal at the sampling time. In an example embodiment, the phase of the clock signal is adjusted in a first direction and a measure of vertical eye opening of the signal is compared to a previous measure. If the measure of vertical eye opening has increased the signal another phase adjustment is made in the same direction and if the vertical eye opening of the signal has decreased a further phase adjustment in the opposite direction is made. By increasing the vertical eye opening of the signal the signal-to-noise ratio of the received signal is improved.
申请公布号 US8761325(B2) 申请公布日期 2014.06.24
申请号 US201012825016 申请日期 2010.06.28
申请人 发明人 Willcocks Ben;Born Chris;Marquina Miguel;Sharratt Andrew;Van Der Horst Allard
分类号 H04L7/00 主分类号 H04L7/00
代理机构 TIPS Group 代理人 TIPS Group
主权项 1. An apparatus for sampling a received digital data signal comprising: a clock generator to generate a clock signal having a phase; a first phase shifter coupled to the clock generator to continuously adjust the phase of the clock signal; a first sampler coupled to the first phase shifter to sample the received signal responsive to the clock signal as phase-adjusted by the first phase shifter; a controller coupled to the first sampler and configured to dither the phase of the clock signal to dynamically maximize the vertical eye opening of the received signal at a sampling time, wherein the controller is configured to determine the vertical eye opening by determining a first signal value that a first predetermined proportion of samples are below and a second signal value that a second predetermined proportion of signal values are below and determine the difference between the first and second signal values; a second phase shifter coupled to the clock generator to adjust the phase of the clock signal; and a second sampler coupled to the second phase shifter to sample the received signal responsive to the clock signal as phase-adjusted by the second phase shifter at the sampling time when the vertical eye opening is maximized to produce an output signal.
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