发明名称 Method, system, and computer program product for implementing multi-power domain digital / mixed signal verification and low power simulation
摘要 Disclosed are a method, system, and computer program product for implementing various embodiments of the methods for implementing multi-power domain digital or mixed-signal verification and low power simulation. The method or the system comprises automatically generating one or more net or terminal expression, set, or one or more overriding net or terminal expression by reading, importing, or interpreting the power data file for the electronic circuit design; identifying one or more schematics of the electronic circuit design; generating an annotated schematic of the electronic circuit design by automatically annotating at least one of the one or more schematics with some of the one or more net or terminal expression, set, or one or more overriding net or terminal expression; and performing verification of the electronic circuit design by using at least the annotated schematic.
申请公布号 US8762906(B2) 申请公布日期 2014.06.24
申请号 US201012752656 申请日期 2010.04.01
申请人 Cadence Design Systems, Inc. 发明人 Ginetti Arnold;O'Riordan Donald J.;Sharma Madhur
分类号 G06F17/50 主分类号 G06F17/50
代理机构 Vista IP Law Group, LLP 代理人 Vista IP Law Group, LLP
主权项 1. A computer implemented method for implementing multi-power domain digital or mixed-signal verification and low power simulation of an electronic circuit design, comprising: using a computer system to perform a process, the process comprising: identifying one or more schematics of the electronic circuit design; generating one or more net or terminal sets or one or more overriding net or terminal sets for the one or more schematics of the electronic circuit design by at least referencing a power data file for the electronic circuit design, wherein the power data file for the electronic circuit design includes a specification of one or more power-saving techniques and data or information for power intent for at least a portion of the electronic circuit design to provide portability of the power intent across multiple electronic circuit design tools; and performing verification or simulation of the electronic circuit design by using at least the one or more net or terminal sets or the one or more overriding net or terminal sets.
地址 San Jose CA US