JFET series connection

摘要

The invention relates to a switching device for switching a current between a first connection (1) and a second connection (2), comprising a series connection of at least two JFETs (J1-J6), of which a lowest JFET (J1) is connected to the first connection (1), or the lowest JFET (J1) is connected in a cascade circuit to the first connection (1) via a control switch (M), and at least one further JFET (J2-J5), which is connected in series to the lowest JFET (J1), wherein the JFET (J6) farthest away from the lowest JFET (J1) is referred to as the uppermost JFET (J6) and is connected with the drain connection to the second connection (2), and wherein a stabilization circuit (D11-D53) is connected between the gate connections of the JFETs (J1-J6) and the first connection (1) in order to stabilize the gate voltages of the JFETs (J1-J6). An additional circuit (4), which draws the potential at the gate connection (G6) of the uppermost JFET (J6) to the potential at the drain connection (D6) of the uppermost JFET (J6), is switched between the gate connection (G6) of the uppermost JFET (J6) and the second connection (2).

主权项

1. A switching device for switching a current between a first connection and a second connection, comprising:
a series connection of at least two JFETs, of which a lowermost JFET is connected to the first connection or the lowermost JFET is connected in a cascode circuit via a control switch to the first connection; at least one further JFET which is connected in series to the lowermost JFET, wherein the JFET which is distanced furthest from the lowermost JFET is indicated as the uppermost JFET and with its drain connection is connected to the second connection; wherein a stabilisation circuit for stabilising the gate voltages of the JFETs is connected between the gate connection of the JFETs and the first connection; wherein an additional circuit is connected between the gate connection of the uppermost JFET and the second connection, and this additional circuit draws the potential at the gate connection of the uppermost JFET to the potential at the drain connection of the uppermost JFET; and wherein a symmetrising network comprising an RC-network arranged between the gates of the JFETs and the first connection is present.