Layout of a MOS array edge with density gradient smoothing

摘要

A multi-step density gradient smoothing layout style is disclosed in which a plurality of unit cells are arranged into an array with a feature density. One or more edges of the array is bordered by a first edge sub-array which has a feature density that is less than the feature density of the array. The first edge sub-array is bordered by second edge sub-array which has a feature density that is less than the feature density of the first edge sub-array, and is approaching that of the background circuitry.

主权项

1. A method of multi-step density gradient smoothing for a semiconductor device array comprising:
arranging a plurality of unit cells into an array, wherein a respective unit cell has a feature density; arranging a plurality of first density gradient cells into a first edge sub-array outside at least part of a perimeter of the array, wherein a respective first density gradient cell has a feature density that is less than the feature density of the unit cell; and arranging a plurality of second density gradient cells into a second edge sub-array outside at least part of a perimeter of the first edge sub-array, wherein a respective second density gradient cell has a feature density that is less than the feature density of the first density gradient cell.