System and method for integrated circuit die size reduction

摘要

A circuit analysis tool is provided for die size reduction analysis. A processor determines a first initial output slack time. If the first initial output slack time is greater than zero, a first circuit element is modeled with a second die area, less than the first die area. The second die area is associated with a third delay greater than the first delay. Then, the second data signal is modeled equal to the first data signal with the third delay. If a first modified output slack time is greater than or equal to zero, the first circuit element first die can be replaced with the second die. If the first modified output slack time is a first value less than zero, a first delay is added to the clock signal that is greater than or equal to the first value.

主权项

1. A circuit analysis tool, enabled with software instructions stored in a computer-readable medium and executable by a processor, for die size reduction analysis, the instructions comprising:
providing a circuit including:
a first circuit element having a signal input to accept a first data signal, and an output to supply a second data signal equal to the first data signal with a first delay, where the first delay is associated with a first die area;a second circuit element having a signal input to accept the second data signal, a clock input to accept a clock signal having a clock frequency, and an output to supply a third data signal equal to the second data signal with a second delay; a processor determining a first initial output slack time; when the first initial output slack time is greater than zero, where a positive slack time indicates the occurrence of the second data signal prior to the occurrence of the clock signal, wherein the clock signal is associated with the second circuit element setup time delay, modeling a first circuit element in second die area, less than the first die area, where the second die area is associated with a third delay greater than the first delay; modeling the second data signal equal to the first data signal with the third delay; and, if a first modified output slack time is greater than or equal to zero, wherein the first modified output slack time is the third delay output; if the first modified output slack time is a first value less than zero, a first delay is added to the clock signal that is greater than or equal to the first value.