| 发明名称 | Matrix operations in an integrated circuit device | ||
| 摘要 | Matrix operations circuitry for performing operations on submatrices of an input matrix includes a first working memory in which individual ones of the submatrices are operated on. The first working memory has a first submatrix size. The matrix operations circuitry also includes a second working memory in which a collection of the submatrices, that have been operated on in the first working memory, is operated on. The second working memory has an optimum burst size, and the first submatrix size is matched to the optimum burst size. | ||
| 申请公布号 | US8762443(B1) | 申请公布日期 | 2014.06.24 |
| 申请号 | US201113296360 | 申请日期 | 2011.11.15 |
| 申请人 | Altera Corporation | 发明人 | Kurtz Brian L. |
| 分类号 | G06F7/32 | 主分类号 | G06F7/32 |
| 代理机构 | Ropes & Gray LLP | 代理人 | Ropes & Gray LLP ;Ingerman Jeffrey H. |
| 主权项 | 1. Matrix operations circuitry for performing operations on submatrices of an input matrix, said matrix operations circuitry comprising: a first working memory in which individual ones of said submatrices are operated on, said first working memory having a first submatrix size; and a second working memory in which a collection of said submatrices, that have been operated on in said first working memory, is operated on, said second working memory having an optimum burst size; wherein: said first submatrix size is matched to said optimum burst size. | ||
| 地址 | San Jose CA US | ||