System and method for reducing cross-coupling noise between charge storage elements in a semiconductor device

摘要

A memory device is provided including a substrate. A first dielectric layer is formed over the substrate. An isolation trench is formed in a portion of the substrate and the first dielectric layer. At least two charge storage elements are formed over the first dielectric layer on opposite sides of the isolation trench. A second dielectric layer is formed over the at least two charge storage elements. A control gate layer is formed over the second dielectric layer, where the isolation trench has a width suitable for reducing cross-coupling noise of charge storage elements, and where the at least two charge storage elements have a height suitable for providing sufficient gate coupling between the at least two charge storage elements and the control gate layer.

主权项

1. A memory device, comprising:
a substrate; a first dielectric layer formed over the substrate; an isolation trench formed in a portion of the substrate and the first dielectric layer; at least two charge storage elements formed over the first dielectric layer on opposite sides of the isolation trench; a second dielectric layer formed over the at least two charge storage elements; and a control gate layer formed over the second dielectric layer, where the isolation trench has a width suitable for reducing cross-coupling noise of charge storage elements, where the at least two charge storage elements have a height suitable for providing sufficient gate coupling between the at least two charge storage elements and the control gate layer, and where a ratio of isolation trench width to charge storage element height ranges from about 20:3 to about 30:1.