发明名称 FinFET device with isolated channel
摘要 Despite improvements in FinFETs and strained silicon devices, transistors continue to suffer performance degradation as device dimensions shrink. These include, in particular, leakage of charge between the semiconducting channel and the substrate. An isolated channel FinFET device prevents channel-to-substrate leakage by inserting an insulating layer between the channel (fin) and the substrate. The insulating layer isolates the fin from the substrate both physically and electrically. To form the isolated FinFET device, an array of bi-layer fins can be grown epitaxially from the silicon surface, between nitride columns that provide localized insulation between adjacent fins. Then, the lower fin layer can be removed, while leaving the upper fin layer, thus yielding an interdigitated array of nitride columns and semiconducting fins suspended above the silicon surface. A resulting gap underneath the upper fin layer can then be filled in with oxide to isolate the array of fin channels from the substrate.
申请公布号 US8759874(B1) 申请公布日期 2014.06.24
申请号 US201213691070 申请日期 2012.11.30
申请人 STMicroelectronics, Inc. 发明人 Loubet Nicolas;Khare Prasanna
分类号 H01L31/0328;H01L31/0336;H01L31/072;H01L31/109 主分类号 H01L31/0328
代理机构 Seed IP Law Group PLLC 代理人 Seed IP Law Group PLLC
主权项 1. A transistor comprising: a silicon substrate; an epitaxial source and drain in contact with a surface of the silicon substrate and formed within an active region located between a pair of insulating trenches extending at least partially into the silicon substrate; a substrate insulating layer in contact with the silicon substrate within an area located between the source and the drain; an array of semiconducting fins positioned between the source and the drain, the array aligned substantially parallel to the trenches, the semiconducting fins selectively electrically coupling the source and the drain while remaining isolated from the silicon substrate by the substrate insulating layer; an array of insulating columns at least partially interdigitated with the array of semiconducting fins, the insulating columns providing localized inter-fin isolation; and a conformal gate overlying, and at least partially contiguous to, three sides of each semiconducting fin, the gate operable to control current flow within the semiconducting fin in response to an applied voltage.
地址 Coppell TX US