Analog-to-digital converter with early interrupt capability

摘要

An early interrupt feature enables generation of interrupts prior to completion of an analog-to-digital conversion to be used in a processor PID calculation. Even though an analog-to-digital conversion is still in process, the PID application software can use the early interrupt time to begin execution of an interrupt service routine (ISR). The early interrupt can improve the throughput and response time of the PID control loop by overlapping the completion of the ADC conversion with the processor overhead associated with the interrupt request. A plurality of pipelined registers, each having substantially the same delay time as the pipelined stages of the ADC, are selectable to provided a delay time that may be used to generate an early interrupt, wherein the latency time between an ADC conversion and processing of an interrupt relating to that ADC conversion may thereby be shortened.

主权项

1. An apparatus for analog-to-digital conversion with early interrupt capability, comprising:
a digital processor and a memory coupled to the digital processor; an interrupt controller coupled to the digital processor, wherein the interrupt controller is adapted to handle interrupts to the digital processor based upon information from a selected analog channel; an analog-to-digital converter (ADC) having a plurality of pipelined stages for converting a sampled analog signal from the selected analog channel to a digital representation thereof; a plurality of pipelined registers arranged to transfer the information from the selected analog channel from one register to a next register at each clock pulse thereto, wherein transfer time through each of the plurality of pipelined registers is substantially the same as delay time through each of the plurality of pipelined stages of the ADC; and a circuit for selecting a one of the plurality of pipelined registers, wherein a conversion ready delay time of the information from the selected analog channel is equal to the delay time at the selected one of the plurality of pipelined registers, whereby the information from the selected analog channel is available to the interrupt controller after the conversion ready delay time.