Bounding box prefetcher

摘要

A data prefetcher in a microprocessor having a cache memory receives memory accesses each to an address within a memory block. The access addresses are non-monotonically increasing or decreasing as a function of time. As the accesses are received, the prefetcher maintains a largest address and a smallest address of the accesses and counts of changes to the largest and smallest addresses and maintains a history of recently accessed cache lines implicated by the access addresses within the memory block. The prefetcher also determines a predominant access direction based on the counts and determines a predominant access pattern based on the history. The prefetcher also prefetches into the cache memory, in the predominant access direction according to the predominant access pattern, cache lines of the memory block which the history indicates have not been recently accessed.

主权项

1. A data prefetcher in a microprocessor having a cache memory, the data prefetcher comprising:
wherein the data prefetcher is configured to receive a plurality of memory accesses each to an address within a memory block, wherein the plurality of memory access addresses are non-monotonically increasing or decreasing as a function of time; a storage element; and control logic, coupled to the storage element, wherein as the plurality of memory accesses are received, the control logic is configured to:
maintain within the storage element a largest address and a smallest address, wherein the largest address specifies a highest address within the memory block of the received memory access addresses, wherein the smallest address specifies a lowest address within the memory block of the received memory access addresses;maintain a count of changes to the largest address and a count of changes to the smallest address, wherein when the control logic changes the largest address the control logic updates the count of changes to the largest address, wherein when the control logic changes the smallest address the control logic updates the count of changes to the smallest address;maintain a history of recently accessed cache lines implicated by the access addresses within the memory block;determine a predominant access direction based on the counts;determine a predominant access pattern based on the history; andprefetch into the cache memory, in the predominant access direction according to the predominant access pattern, cache lines of the memory block which the history indicates have not been recently accessed.