发明名称 Memory device and electronic device
摘要 A selection operation is performed for individual memory cells. A device includes a first memory cell and a second memory cell provided in the same row as the first memory cell, each of which includes a field-effect transistor having a first gate and a second gate. The field-effect transistor controls at least data writing and data holding in the memory cell by being turned on or off. The device further includes a row selection line electrically connected to the first gates of the field-effect transistors included in the first memory cell and the second memory cell, a first column selection line electrically connected to the second gate of the field-effect transistor included in the first memory cell, and a second column selection line electrically connected to the second gate of the field-effect transistor included in the second memory cell.
申请公布号 US8760959(B2) 申请公布日期 2014.06.24
申请号 US201213418546 申请日期 2012.03.13
申请人 Semiconductor Energy Laboratory Co., Ltd. 发明人 Matsubayashi Daisuke
分类号 G11C8/00;G11C8/10 主分类号 G11C8/00
代理机构 Fish & Richardson P.C. 代理人 Fish & Richardson P.C.
主权项 1. A memory device comprising: a first memory cell; a second memory cell provided in a same row as the first memory cell; a row selection line; a first column selection line; and a second column selection line, wherein the first memory cell includes a field-effect transistor comprising a first gate and a second gate and controlling at least data writing and data holding in the first memory cell by being turned on or off, wherein the second memory cell includes a field-effect transistor comprising a first gate and a second gate and controlling at least data writing and data holding in the second memory cell by being turned on or off, wherein the row selection line is electrically connected to the first gates of the field-effect transistors included in the first memory cell and the second memory cell, wherein the first column selection line is electrically connected to the second gate of the field-effect transistor included in the first memory cell, and wherein the second column selection line is electrically connected to the second gate of the field-effect transistor included in the second memory cell.
地址 Atsugi-shi, Kanagawa-ken JP