发明名称 Continuous time delta sigma converter having a VCO based quantizer
摘要 A continuous-time delta sigma converter includes a loop filter having a plurality of serially coupled integrators including a first integrator responsive to an input of the Delta Sigma converter and a last integrator responsive to a first feedback loop and providing an integrated output signal, and a voltage controlled oscillator (VCO) based quantizer responsive to the loop filter for integrating the integrated output signal and providing a digital output signal. The first feedback loop includes a first time delay circuit responsive to the output of the quantizer and at least one switched capacitor digital to analog converter (DAC) responsive to the first time delay circuit. The first feedback loop is configured to differentiate the digital output signal twice and provide the last integrator of the loop filter with a double differentiated analog signal to reduce excess loop delay.
申请公布号 US8760331(B2) 申请公布日期 2014.06.24
申请号 US201213542691 申请日期 2012.07.06
申请人 Hittite Microwave Norway AS 发明人 Kaald Rune
分类号 H03M3/00 主分类号 H03M3/00
代理机构 Iandiorio Teska & Coleman, LLP 代理人 Iandiorio Teska & Coleman, LLP
主权项 1. A continuous-time delta sigma converter, comprising: a loop filter including a plurality of serially coupled integrators including a first integrator responsive to an input of the Delta Sigma converter and a last integrator responsive to a first feedback loop and providing an integrated output signal; and a voltage controlled oscillator (VCO) based quantizer responsive to the loop filter for integrating the integrated output signal and providing a digital output signal; the first feedback loop including a first time delay circuit responsive to the output of the quantizer and at least one switched capacitor digital to analog converter (DAC) responsive to the first time delay circuit, the first feedback loop configured to differentiate the digital output signal twice and provide the last integrator of the loop filter with a double differentiated analog signal to reduce excess loop delay.
地址 Tiller NO