发明名称 APPARATUS AND METHOD FOR PREDICTING PERFORMANCE ATTRIBUTABLE TO PARALLELIZATION OF HARDWARE ACCELERATION DEVICES
摘要 Disclosed herein are an apparatus and method for predicting performance attributable to the parallelization of hardware acceleration devices. The apparatus includes a setting unit, an operation unit, and a prediction unit. The setting unit divides the time it takes to perform a task into a plurality of task stages and processing stages, and sets one of a parallelization index and target performance. The operation unit calculates the times it takes to perform the stages, and calculates at least one of the ratio of a target parallelization stage in the task and a speed improvement value. The prediction unit calculates an expected performance value or a parallelization index based on at least one of the calculated the times it takes to perform the stages, the calculated ratio of the target parallelization stage, the calculated speed improvement value, and the set target performance.
申请公布号 US2014173608(A1) 申请公布日期 2014.06.19
申请号 US201313953993 申请日期 2013.07.30
申请人 ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE 发明人 JEONG Jin-Hwan
分类号 G06F9/46 主分类号 G06F9/46
代理机构 代理人
主权项 1. An apparatus for predicting performance attributable to parallelization of hardware acceleration devices, comprising: a setting unit configured to divide a time it takes to perform a task into a plurality of task stages and a plurality of processing stages based on a target module to be parallelized, and to set one of a parallelization index and target performance; an operation unit configured to calculate a time it takes to perform each of the plurality of task stages and the plurality of processing stages, and to calculate at least one of a ratio of a target parallelization stage in the task and a speed improvement value based on the calculated times; and a prediction unit configured to calculate an expected performance value or a parallelization index based on at least one of the calculated times it takes to perform the plurality of task stages and the plurality of processing stages, the calculated ratio of the target parallelization stage, the calculated speed improvement value, and the set target performance.
地址 Daejeon-city KR