VERTICAL NANOWIRE TRANSISTOR WITH AXIALLY ENGINEERED SEMICONDUCTOR AND GATE METALLIZATION

摘要

Vertically oriented nanowire transistors including semiconductor layers or gate electrodes having compositions that vary over a length of the transistor. In embodiments, transistor channel regions are compositionally graded, or layered along a length of the channel to induce strain, and/or include a high mobility injection layer. In embodiments, a gate electrode stack including a plurality of gate electrode materials is deposited to modulate the gate electrode work function along the gate length.

主权项

1. A vertical nanowire transistor having a longitudinal axis perpendicularly oriented to a surface plane of a crystalline substrate, the transistor comprising:
a group IV or group III-V epitaxial source semiconductor layer vertically aligned with an epitaxial group IV or group III-V drain semiconductor layer along the longitudinal axis; a group IV or group III-V epitaxial channel semiconductor layer disposed between source and drain semiconductor layers, the channel semiconductor layer having an epitaxial film thickness associated with a channel length of the transistor; and an annular gate electrode surrounding a sidewall of the semiconductor channel layer, separated by an annular gate dielectric layer, and wherein the composition of at least one of the gate electrode or the semiconductor layers varies along the longitudinal axis.