POWER STORAGE SYSTEM AND POWER STORAGE DEVICE

摘要

The versatility of a power feeding device is improved. A power storage system includes a power storage device and a power feeding device. The power storage device includes data for identifying the power storage device. The power storage device includes a power storage unit, a switch that controls whether power from the power feeding device is supplied to the power storage unit, and a control circuit having a function of controlling a conduction state of the switch in accordance with a control signal input from the power feeding device. The power feeding device includes a signal generation circuit having a function of identifying the power storage device by the data input from the power storage device, generating the control signal corresponding to the identified power storage device, and outputting the generated control signal to the power storage device.

主权项

1. A power storage device comprising:
a power receiving circuit; a data communication circuit; a power storage unit; a first transistor between the power receiving circuit and the power storage unit; and a control circuit electrically connected to a gate of the first transistor and to the power storage unit, wherein the control circuit includes: a processor that includes a register and is electrically connected to the gate of the first transistor; a memory that includes data for identifying the power storage device and is electrically connected to the processor; and a controller electrically connected to the processor and to the memory, wherein the register includes: a first memory circuit configured to hold data in a period during which power is supplied to the processor from the power storage unit; and a second memory circuit configured to hold data in a period during which supply of the power to the processor from the power storage unit is stopped, the second memory circuit including a second transistor configured to control writing and holding of data, and wherein an off-state current per micrometer of channel width of the second transistor is lower than or equal to 100 zA.