发明名称 OPTICAL INTERCONNECT ON BUMPLESS BUILD-UP LAYER PACKAGE
摘要 This disclosure relates generally to an electronic package that can include a die and a dielectric layer at least partially enveloping the die. Electrical interconnects can be electrically coupled to the die and passing, at least in part, through the dielectric layer. An optical emitter can be electrically coupled to the die with a first one of the electrical interconnects and configured to emit light from a first major surface of the electronic package. A solder bump can be electrically coupled to the die with a second one of the electrical interconnects and positioned on a second major surface of the electronic package different from the first major surface.
申请公布号 US2014169800(A1) 申请公布日期 2014.06.19
申请号 US201213717185 申请日期 2012.12.17
申请人 Eid Feras;Swan Johanna;Teh Weng Hong 发明人 Eid Feras;Swan Johanna;Teh Weng Hong
分类号 H04B10/40;F21V21/00;H01L33/00 主分类号 H04B10/40
代理机构 代理人
主权项 1. A method of making a chip package, comprising: electrically coupling electrical interconnects to a die; forming a buildup layer that substantially envelops the die and the electrical interconnects; electrically coupling an optical emitter to a first one of the electrical interconnects, wherein the optical emitter is electrically coupled to the die, and wherein the optical emitter is configured to emit light from a first major surface of the chip package; and forming a solder bump coupled to a second one of the electrical interconnects and electrically coupled to the die, wherein the solder bump is positioned on a second major surface of the chip package.
地址 Chandler AZ US