MULTI-FREQUENCY CLOCK SKEW CONTROL FOR INTER-CHIP COMMUNICATION IN SYNCHRONOUS DIGITAL SYSTEMS

摘要

Embodiments are disclosed of a multi-chip apparatus capable of performing multi-rate synchronous communication between component chips. Each chip may receive a common clock reference signal, and may generate an internal clock signal dependent on the clock reference signal. A clock distribution tree and phase-locked loop may be used to minimize internal clock skew at I/O circuitry at the chip perimeter. Each chip may also generate an internal synchronizing signal that is phase-aligned to the received clock reference signal. Each chip may use its respective synchronizing signal to synchronize multiple clock dividers that provide software-selectable reduced-frequency clock signals to the I/O cells of the chip. In this way, the reduced-frequency clock signals of the multiple chips are edge-aligned to the low-skew internal clock signals, and phase-aligned to the common clock reference signal, allowing the I/O cells of the multiple chips to perform synchronous communication at multiple rates with low clock skew.

主权项

1. An apparatus comprising:
a reference clock generator configured to generate a reference clock signal; and a plurality of integrated circuit chips, each chip comprising:
an input port coupled to the reference clock generator, wherein the input port is configured to receive the reference clock signal;clock generation circuitry configured to generate a primary clock signal dependent upon the reference clock signal;synchronizing signal generation circuitry configured to generate a synchronizing signal that is edge-aligned to the primary clock signal dependent upon the reference clock signal, wherein the respective synchronizing signals of the plurality of chips are phase-aligned as a result of their common dependence upon the reference clock signal;clock divider circuitry configured to:
receive a delayed version of the primary clock signal and a delayed version of the synchronizing signal; andgenerate a frequency-divided clock signal having a frequency that is less than a frequency of the delayed version of the primary clock signal, wherein the frequency-divided clock signal is edge-aligned to the delayed version of the primary clock signal and phase-aligned to the delayed version of the synchronizing signal; andinput/output (I/O) circuitry configured to:
receive as a clock input the frequency-divided clock signal; andcommunicate with the respective I/O circuitry of another chip of the plurality of chips, wherein the frequency of the frequency-divided clock signal is the same as the respective frequency of the frequency-divided clock signal of the other chip, and wherein the frequency-divided clock signal is phase-aligned with the respective frequency-divided clock signal of the other chip.