INTERFACE PROTECTION DEVICE WITH INTEGRATED SUPPLY CLAMP AND METHOD OF FORMING THE SAME

摘要

Protection circuit architectures with integrated supply clamps and methods of forming the same are provided herein. In certain implementation, an integrated circuit interface protection device includes a first diode protection structure and a first thyristor protection structure electrically connected in parallel between a signal pin a power high supply. Additionally, the protection device includes a second diode protection structure and a second thyristor protection structure electrically connected in parallel between the signal pin and a power low supply. Furthermore, the protection device includes a third diode protection structure and a third thyristor protection structure electrically connected in parallel between the power high supply and the power low supply. The third thyristor protection structure and the third diode protection structure are synthesized as part of the integrated circuit interface and can share at least a portion of the wells and/or diffusion regions associated with the first and second thyristor protection structures.

主权项

1. An integrated circuit comprising:
a power high pin configured to receive a first supply voltage; a power low pin configured to receive a second supply voltage; a signal pin configured to receive a signal; a first NPN bipolar transistor including an emitter electrically connected to the signal pin; a first PNP bipolar transistor including an emitter electrically connected to the power high pin, wherein the first PNP bipolar transistor and the first NPN bipolar transistor are cross-coupled and configured to operate as a first thyristor protection structure between the power high pin and the signal pin; a second NPN bipolar transistor including an emitter electrically connected to the power low pin; a third NPN bipolar transistor including an emitter electrically connected to the power low pin; a second PNP bipolar transistor including an emitter electrically connected to the signal pin, wherein the second PNP bipolar transistor and the third NPN bipolar transistor are cross-coupled and configured to operate as a second thyristor protection structure between the signal pin and the power low pin, wherein the first PNP bipolar transistor and the second NPN bipolar transistor are cross-coupled and configured operate as a third thyristor protection structure between the power high pin and the power low pin.