DEVICE STRUCTURE WITH INCREASED CONTACT AREA AND REDUCED GATE CAPACITANCE

摘要

A FET structure including epitaxial source and drain regions includes large contact areas and exhibits both low resistivity and low parasitic gate to source/drain capacitance. The source and drain regions are laterally etched to provide recesses for accommodating low-k dielectric material without compromising the contact area between the source/drain regions and their associated contacts. A high-k dielectric layer is provided between the raised source/drain regions and a gate conductor as well as between the gate conductor and a substrate, such as an ETSOI or PDSOI substrate. The structure is usable in electronic devices such as MOSFET devices.

主权项

1. A method comprising:
obtaining a semiconductor-on-insulator substrate; forming a sacrificial gate layer on the substrate; forming doped raised source and drain regions on the substrate, each raised source and drain region having a top surface and a bottom surface; removing the sacrificial gate layer, thereby forming a space between the raised source and drain regions; laterally etching the raised source and drain regions to form laterally expanded recesses extending from the space into the raised source and drain regions, and filling the space with a first dielectric material.