INTERFACE PROTECTION DEVICE WITH INTEGRATED SUPPLY CLAMP AND METHOD OF FORMING THE SAME

摘要

Protection circuit architectures with integrated supply clamps and methods of forming the same are provided herein. In certain implementation, an integrated circuit interface protection device includes a first diode protection structure and a first thyristor protection structure electrically connected in parallel between a signal pin a power high supply. Additionally, the protection device includes a second diode protection structure and a second thyristor protection structure electrically connected in parallel between the signal pin and a power low supply. Furthermore, the protection device includes a third diode protection structure and a third thyristor protection structure electrically connected in parallel between the power high supply and the power low supply. The third thyristor protection structure and the third diode protection structure are synthesized as part of the integrated circuit interface and can share at least a portion of the wells and/or diffusion regions associated with the first and second thyristor protection structures.

主权项

1. An apparatus comprising:
a substrate; a first well region of a first type in the substrate; a second well region of the first type in the substrate adjacent the first well region; a third well region of a second type opposite the first type, wherein the third well region is positioned in the substrate between the first and second well regions; a fourth well region of the second type positioned on a side of the first well region that is opposite the third well region; a first diffusion region of the first type in the fourth well region; a second diffusion region of the second type in the first well region; a third diffusion region of the first type in the third well region; a fourth diffusion region of the second type in the second well region, wherein the first diffusion region, the fourth well region, the first well region, and the second diffusion region are configured to operate as a first thyristor structure, wherein the third diffusion region, the third well region, the second well region, and the fourth diffusion region are configured to operate as a second thyristor structure, and wherein the second diffusion region, the first well region, the third well region and the third diffusion region are configured to operate as a third thyristor structure.