METHOD FOR GENERATING A TOPOGRAPHY OF AN FDSOI INTEGRATED CIRCUIT

摘要

An IC including first and second FDSOI UTBOX cells arranged in a row, the first having an nMOS transistor arranged plumb with and above a ground plane and an N-type well, and a pMOS transistor arranged plumb with and above a ground plane and a P-type well, the N-type well and the P-type well being arranged on either side of a row axis, wherein the second includes a diode protecting against antenna effects or a well tap cell, the second cell comprising a P-type well arranged in the alignment of the P-type well of the pMOS transistor and comprising an N-type well arranged in the alignment of the N-type well of the nMOS transistor, the second cell comprising a metal connection coupled to its P-type well and coupled to a higher-level metal connection element arranged plumb with the N-type well, the metal connection extending on either side of the axis.

主权项

1. A method for generating a digital integrated circuit topography, said method comprising automatically placing standard cells in a row of a topography of said integrated circuit, said standard cells comprising a first standard cell and a second standard cell, wherein said first standard cell includes an nMOS transistor disposed plumb with a P-type doping well, and a pMOS transistor disposed plumb with an N-type doping well, said P-type well and said N-type well being arranged on either side of an axis of said row, and wherein said second standard cell includes one of a diode protecting against antenna effects and a well tap cell, said second standard cell comprising a P-type doping well arranged in an alignment of said P-type well of said nMOS transistor and comprising an N-type doping well arranged in an alignment of said N-type well of said pMOS transistor, said second standard cell comprising a lower metal connection element coupled to said P-type doping well thereof, automatically routing said standard cells, wherein automatically routing comprises creating an interconnection between said lower metal connection element and an upper metal connection element arranged plumb with said lower metal connection element, replacing said second standard cell with a third standard cell comprising a P-type doping well arranged in said alignment of said P-type well of said nMOS transistor and comprising an N-type doping well arranged in said alignment of said N-type well of said pMOS transistor, said third cell comprising a lower metal connection element extending on either side of said axis and coupled to said N-type doping well and coupled to said upper metal connection element, automatically inverting said doping type of said wells of said first and third standard cells, and generating a digital topography of etching masks for manufacture of an FDSOI UTBOX integrated circuit including said first and third standard cells having been subjected to said automatic doping inversion.