PARITY DATA MANAGEMENT FOR A MEMORY ARCHITECTURE

摘要

A processor system as presented herein includes a processor core, cache memory coupled to the processor core, a memory controller coupled to the cache memory, and a system memory component coupled to the memory controller. The system memory component includes a plurality of independent memory channels configured to store data blocks, wherein the memory controller controls the storing of parity bits in at least one of the plurality of independent memory channels. In some implementations, the system memory is realized as a die-stacked memory component.

主权项

1. A memory system comprising:
at least one die-stacked memory component comprising a plurality of stacked memory devices arranged to provide a plurality of independent memory channels and at least one parity channel; wherein the at least one parity channel is utilized to store parity bits for the plurality of independent memory channels.