MEMORY BIT MBIST ARCHITECTURE FOR PARALLEL MASTER AND SLAVE EXECUTION

摘要

A scalable, reconfigurable Memory Built-In Self-Test (MBIST) architecture for a semiconductor device, such as a multiprocessor, having a Master and one or more Slave MBIST controllers is described. The MBIST architecture includes a plurality of MBISTDP interfaces connected in a ring with the Master MBIST controller. Each MBISTDP interface connects to at least one Slave controller for forwarding test information streamed to it from the Master MBIST controller over the ring. Test information includes test data, address, and MBIST test commands. Each MBISTDP interface forwards the information to the Slave controller attached thereto and to the next MBISTDP interface on the ring. Test result data is sent back to the Master MBIST controller from the MBISTDP interfaces over the ring.

主权项

1. An apparatus having a built-in self-test (BIST) architecture comprising:
a master controller for controlling built-in self-testing of a device; two or more BIST Data Path (BISTDP) interfaces (I/Fs) connected in a ring to the master controller; and two or more slave controllers, each connected to a BISTDP I/F for receiving test commands from the master controller and for conducting built-in self-testing, each slave controller configured to test at least a portion of a circuit.