发明名称 |
INFORMATION PROCESSING APPARATUS AND SCHEDULING METHOD |
摘要 |
An information processing apparatus includes: at least one access unit that issues a memory access request for a memory; an arbitration unit that arbitrates the memory access request issued from the access unit; a management unit that allows the access unit that is an issuance source of the memory access request according to a result of the arbitration made by the arbitration unit to perform a memory access to the memory; a processor that accesses the memory through at least one cache memory; and a timing adjusting unit that holds a process relating to the memory access request issued by the access unit for a holding time set in advance and cancels the holding of the process relating to the memory access request in a case where power of the at least one cache memory is turned off in the processor before the holding time expires. |
申请公布号 |
US2014173202(A1) |
申请公布日期 |
2014.06.19 |
申请号 |
US201414184419 |
申请日期 |
2014.02.19 |
申请人 |
FUJITSU LIMITED |
发明人 |
KOIKE NOBUYUKI;MIYAMOTO Toshihiro |
分类号 |
G06F12/08;G06F13/16 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
1. An information processing apparatus comprising:
at least one access unit that issues a memory access request for a memory; an arbitration unit that arbitrates the memory access request issued from the access unit; a management unit that allows the access unit that is an issuance source of the memory access request according to a result of the arbitration made by the arbitration unit to perform a memory access to the memory; a processor that accesses the memory through at least one cache memory; and a timing adjusting unit that holds a process relating to the memory access request issued by the access unit for a holding time set in advance and cancels the holding of the process relating to the memory access request in a case where power of the at least one cache memory is turned off in the processor before the holding time expires.
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地址 |
Kawasaki-shi JP |