SOURCE/DRAIN EXTENSION CONTROL FOR ADVANCED TRANSISTORS

摘要

A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×1019 atoms/cm3, or alternatively, less than one-quarter the dopant concentration of the source and the drain.

主权项

1. A semiconductor die, comprising:
a plurality of transistors, the plurality of transistors each having:
a gate with an effective gate length;a source region;a drain region;an epitaxially grown channel layer below the gate and extending between the source region and the drain region;a first highly doped layer below the channel layer and coextensive therewith, the first highly doped layer effective to set a depletion depth for said plurality of transistors; and wherein some of the plurality of transistors have a second highly doped layer below the channel layer and above the first highly doped layer; wherein some of the plurality of transistors include a source and drain extension region; and wherein some of the plurality of transistors are haloless.