MEMORY CONTROLLER AND OPERATING METHOD OF THE SAME

摘要

The present invention relates to a memory controller which performs error bit correction. The memory controller according to embodiments of the present invention comprises: a register for storing a parity check matrix; and an error correcting code (ECC) decoder which performs error bit correction on data provided from a non-volatile memory device using the parity check matrix. The parity check matrix includes N column matrices, where N is a natural number. Each of the N column matrices includes multiple sub-matrices, which is a non-zero valued matrix that comes last in an decoding sequence of the ECC decoder, and is an identity matrix.