MULTI-CORE PROCESSING DEVICE WITH INVALIDATION CACHE TAGS AND METHODS

摘要

A data processing device is provided that facilitates cache coherence policies. In one embodiment, a data processing device utilizes invalidation tags in connection with a cache that is associated with a processing engine. In some embodiments, the cache is configured to store a plurality of cache entries where each cache entry includes a cache line configured to store data and a corresponding cache tag configured to store address information associated with data stored in the cache line. Such address information includes invalidation flags with respect to addresses stored in the cache tags. Each cache tag is associated with an invalidation tag configured to store information related to invalidation commands of addresses stored in the cache tag. In such embodiment, the cache is configured to set invalidation flags of cache tags based upon information stored in respective invalidation tags.

主权项

1. A data processing device comprising:
a cache associated with a processing engine; the cache configured to store a plurality of cache entries; each cache entry including a cache line configured to store data and a corresponding cache tag configured to store address information associated with data stored in the cache line where the address information includes an invalidation flag with respect to each address stored in the cache tag; each cache tag associated with an invalidation tag configured to store information related to invalidation commands of addresses stored in the cache tag; and the cache configured to set invalidation flags of cache tags based upon information stored in respective invalidation tags.