HTO OFFSET FOR LONG LEFFECTIVE, BETTER DEVICE PERFORMANCE

摘要

Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.

主权项

1. A dual-bit memory cell comprising:
a charge trapping dielectric stack disposed overlying a semiconductor substrate; a poly gate disposed overlying the charge trapping dielectric stack; pocket implant regions adjacent and under the charge trapping dielectric stack; bit lines in the semiconductor substrate adjacent the charge trapping dielectric stack and under bit line openings; and a word line.