发明名称 Verification module apparatus for debugging software and timing of an embedded processor design that exceeds the capacity of a single FPGA
摘要 <p>A plurality of Field Programmable Gate Arrays (FPGA), high performance transceivers, and memory devices provide a verification module for timing and state debugging of electronic circuit designs. Signal value compression circuits and gigabit transceivers embedded in each FPGA increase the fanout of each FPGA. Ethernet communication ports enable remote software debugging of processor instructions.</p>
申请公布号 EP2743848(A1) 申请公布日期 2014.06.18
申请号 EP20130194972 申请日期 2013.11.28
申请人 S2C INC. 发明人 CHENE, MON-REN
分类号 G06F17/50 主分类号 G06F17/50
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