Impulsverzoegerungsschaltung

摘要

885,723. Transistor pulse delaying circuits. PHILIPS ELECTRICAL INDUSTRIES Ltd. April 16, 1958 [April 18, 1957], No. 12162/58. Class 40(6). In a pulse delay circuit comprising a transistor having a resistor arranged in series in its collector-emitter circuit, a short pulse which is to be delayed is applied to the emitter-base circuit of the transistor in such a sense as to render the emitter-base path conductive while a longer pulse having a width greater than the desired delay and whose leading edge coincides with that of the short pulse is applied through the resistor in a sense to reverse the bias to the collector-base diode of the transistor, whereby, owing to charge storage in the base zone of the transistor, the collector-emitter path of the transistor remains conductive for a predetermined time after the termination of the short pulse, the change in potential at one electrode of the transistor occurring at the end of this interval being used to generate (e.g. by differentiation) a delayed pulse. In a first embodiment, Fig. 1, a short pulse to be delayed is applied from a source 5 through a transformer 3 to the emitter-base path of the transistor 1 while a longer negative pulse derived from a source 7, which may for example, be a monostable trigger circuit, is applied through a resistor 6 to the collector electrode of the transistor. Owing to charge storage the transistor remains bottomed for a predetermined interval after the termination of the short pulse with the collector remaining substantially at earth potential. When, however, the charge carriers have been swept from the base of the transistor 1 by the long negative pulse, the collector potential rises negatively and a delayed pulse is supplied at the output terminals by means of a differentiating circuit 8, 9. In a further circuit, Fig. 3, the pulse to be delayed is derived by differentiation in the transformer 31 of the long pulse, the latter being applied to the collector-emitter circuit of the transistor 1 through a resistor 6 connected in this case to the emitter electrode of the transistor. The output of the circuit is applied to an integrating circuit 11, 12 which removes small pulses from the output signal and is then applied to a transistor amplifier 13 the output of which is differentiated to produce the delayed pulse by means of a circuit 14, 16. A small bias voltage source may be arranged in the emitter circuit of the collector 13 in order to improve the form of the pulse delivered at the output 10 and also to ensure that the transistor 13 'is rendered conductive only by positive pulses having an amplitude greater than the bias voltage. In a third embodiment, Fig. 4 (not shown), the pulse to be delayed is derived from the long pulse by means of a condenser resistor differentiating circuit. The resulting delayed pulse is then applied to an emitterfollower output stage. Specifications 827,666 and 835,907 are referred to.