Stacked packages having through hole vias

摘要

Provided is a method of forming a package-on-package. An encapsulation is formed to cover a wafer using a wafer level molding process. The wafer includes a plurality of semiconductor chips and a plurality of through silicon vias (TSVs) passing through the semiconductor chips. The encapsulant may have openings aligned with the TSVs. The encapsulant and the semiconductor chips are divided to form a plurality of semiconductor packages. Another semiconductor package is stacked on one selected from the semiconductor packages. The other semiconductor package is electrically connected to the TSVs.

主权项

1. A semiconductor package, comprising:
a first semiconductor package, the first semiconductor package including a first semiconductor chip having a plurality of through silicon vias (TSVs) extending therethrough, a plurality of internal connection terminals in a form of a conductive bump or a solder ball on the plurality of TSVs, and an encapsulant on the first semiconductor chip and the plurality of internal connection terminals, the encapsulant including a plurality of openings corresponding to the plurality of interconnection terminals; and a second semiconductor package on the first semiconductor package, the second semiconductor package including a second semiconductor chip and a plurality of external connection terminals, the plurality of—external connection terminals protruding into the openings to electrically connect the first semiconductor chip to the second semiconductor chip, wherein a sidewall of the encapsulant is coplanar with a sidewall of the first semiconductor chip.