Multirank DDR memory modual with load reduction

摘要

A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The memory module has a first number of ranks of double-data-rate (DDR) memory devices activated at least in part to a first number of chip-select signals. The circuit is configurable to receive address signals and a second number of chip-select signals from the computer system. The circuit is further configurable to generate and transmit phase-locked clock signals to the first number of ranks, and to generate the first number of chip-select signals in response at least in part to the phase-locked clock signals, the address signals, and the second number of chip-select signals.

主权项

1. A memory module to be coupled to a memory controller via a plurality of signal lines, including input control signal lines, DQ data signal lines and DQS data strobe signal lines, the memory module comprising:
a first logic element to receive input control signals associated with a first memory command from the memory controller via the input control signal lines, and to generate output control signals in response to the input control signals; memory devices organized in a number of ranks including a first rank receiving a first set of one or more of the output control signals and at least one second rank receiving at least one second set of one or more of the output control signals, wherein a first memory device in the first rank and at least one second memory device in the at least one second rank communicate with the memory controller via a common set of the DQ and DQS signal lines among the plurality of signal lines; and a second logic element to selectively enable data communication between the first memory device and the memory controller via the common set of the DQ and DQS signal lines in response to the first memory command while isolating a load associated with the at least one second memory device from the common set of the DQ and DQS signal lines; wherein the first logic element is configured to determine a latency value based on a previous memory command received by the memory module from the memory controller, and wherein the first logic element controls the second logic element to selectively enable the data communication according to the latency value.