Data receiving device, semiconductor integrated circuit, and method for controlling data receiving device

摘要

A data receiving device capable of reducing power consumption. A data receiving device according to the present invention has a receiving circuit and a power reduction circuit. The receiving circuit includes a receiver for receiving differential signals, a decode circuit, and a control circuit. The power reduction circuit puts the receiver into an on state in accordance with timing of a data reception start by the receiving circuit, and puts the receiver into an off state in accordance with timing of a data reception end by the receiving circuit. Further, the control circuit puts the power reduction circuit into an off state in accordance with the timing of the data reception start by the receiving circuit, and puts the power reduction circuit into an on state in accordance with the timing of the data reception end by the receiving circuit.

主权项

1. A data receiving device comprising:
a receiving circuit including a receiver that receives differential signals, a decode circuit that decodes a signal outputted from the receiver, and a control circuit to which data outputted from the decode circuit is supplied; and a power reduction circuit that reduces power consumption of the receiving circuit, wherein the power reduction circuit puts the receiver into an on state in accordance with timing of a data reception start by the receiving circuit, and puts the receiver into an off state in accordance with timing of a data reception end by the receiving circuit, wherein the control circuit puts the power reduction circuit into an off state in accordance with the timing of the data reception start by the receiving circuit, and puts the power reduction circuit into an on state in accordance with the timing of the data reception end by the receiving circuit, wherein the power reduction circuit includes
a first single-end buffer to which one of the differential signals is supplied;a second single-end buffer to which the other differential signal is supplied; anda state monitoring circuit which puts the receiver into the on state or the off state in accordance with output from the first and second single-end buffers, and wherein the control circuit in the receiving circuit includes
an analysis circuit that analyzes a packet of data outputted from the decode circuit and acquires a packet length of the data; anda first enable signal generation circuit that generates an enable signal for putting the first and second single-end buffers into an off state if the packet length acquired by the analysis circuit is greater than a predetermined packet length.